Method and apparatus for testing eye diagram characteristics

ABSTRACT

The present invention discloses a method and apparatus for testing eye diagram characteristics. The present invention does not utilize a RF analyst used in prior art. On the contrary, the present invention directly sends a precondition from a mainframe to a chip under test, and the GLPF signals are read out from the chip under test. After digitalizing and normalizing the GLPF signals, an eye diagram program stored in the mainframe is executed and the eye diagram is reconstructed. Next, a software analyzer is used to compute an error between the eye diagram parameters and predefined specifications, to determine if the chip under test is in an allowable range of the specification according to the computed error. If the computed error is beyond the allowable range, the chip under test will be discarded.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and apparatus for testing acommunication chip, and particularly to a method and apparatus fortesting eye diagram characteristics of a communication chip.

2. Description of Related Art

For communication chips or system single chips, it is necessary to testthe quality of eye diagram characteristics for the output signals of theGuassian Low Pass Filter (GLPF) of the transmitter before leaving thefactory so as to pick out defective products. In the stage of researchand engineering verification, engineers always use an oscilloscope or anRF analyst (such as HP 71501A) to check by hand if the eye diagramcharacteristics of the communication chips fit the requirement ofspecifications. However, in the stage of testing products, if the workis done by hand, it will slow down the output of products and increasethe test cost.

FIG. 1 shows a prior art testing apparatus, including a mainframe 11, anRF analyst 15, a chip under test 14 and a mechanical arm 12. The chipunder test 14 is placed on a testing plate 13 of the mechanical arm 12.First, the mainframe 11 issues a precondition to the chip under test 14,and drives the chip under test 14 output GLPF signals to the RF analyst15. The RF analyst 15 transfers the GLPF signals into an eye diagram,and the workers check if the chip under test 14 fits specificationsthrough a screen examination.

However, the above method cannot be made automatic so that a testingcycle of a chip will take a lot of time and lessen the output ofproducts. Second, the RF analyst 15 is so expensive that the totaltesting cost is high. Third, due to man's neglects or an inaccuratecomparison under an eyesight limitation, the defective chips cannotalways be picked out by hand and errors are bound to happen.

To eliminate the disadvantages of the prior art, the present inventionproposes a novelty method and apparatus for testing eye diagramcharacteristics to overcome the above drawbacks.

SUMMARY OF THE INVENTION

A main object of the present invention is to provide an automatic and acost-down method and apparatus for testing eye diagram characteristics.

The second object of the present invention is to provide a method andapparatus for fast testing eye diagram characteristics.

To obtain the above purpose, the present invention does not utilize anRF analyst as used in prior art. On the contrary, the present inventiondirectly sends a precondition from a mainframe to a chip under test, andthe GLPF signals are read out from the chip under test. Afterdigitalizing and normalizing the GLPF signals, an eye diagram programstored in the mainframe is executed and the eye diagram isreconstructed. Next, a software analyzer is used to compute an errorbetween the eye diagram parameters and predefined specifications, anddetermining if the chip under test is in an allowable range of thespecification according to the computed error. If the computed error isbeyond the allowable range, the chip under test will be discarded.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be described according to the appendeddrawings in which:

FIG. 1 shows a prior art testing apparatus;

FIG. 2 shows an embodiment of a testing apparatus according to thepresent invention;

FIG. 3 shows a testing flow diagram of the present invention;

FIG. 4 shows a reconstruction flow of the eye diagram according to thepresent invention; and

FIG. 5 shows a hint figure of an eye diagram.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

FIG. 2 shows an embodiment of a testing apparatus according to thepresent invention. The testing apparatus includes a mainframe 21, a chipunder test 24 and a mechanical arm 22. The chip under test 24 is placedon a testing plate 23 of the mechanical arm 22. The characteristic ofthe present invention is that the mainframe 21 is an Automatic TestingEquipment (ATE), therefore inside of the mainframe 21 is a computinghardware (such as a workstation) which could be parameters and softwareprograms inputted by users. Generally speaking, the mainframe 21includes three modules a digitizer 25, an eye diagram reconstructionmeans 26 and an error comparison means 27. The digitizer 25 is used tocapture GLPF output signals of the chip under test 24, and furtherdigitizing and normalizing the GLPF output signals. The eye diagramreconstruction means 26 is used to overlap the captured signals in acycle time to form an eye diagram. The error comparison means 27 is usedto calculate if errors of parameters of the eye diagram are in anallowable range. If the answer is no, the defective product should bediscarded.

FIG. 3 shows a testing flow diagram of the present invention. In step31, the present invention starts. In step 32, the mainframe 21 sendspreconditions to the chip under test 24, and reads GLPF signals from thechip under test 24. Generally speaking, the present invention couldcapture signals from about thousands of test cycles according to a testperiod. In step 33, the GLPF signals are digitalized and normalized. Instep 34, an eye diagram is constructed according to the steps shown inFIG. 4. In step 35, the parameters (such as a width, height, crossratio, RMS-Jitter of the eye) of the eye diagram are first computed, andthen the errors between the parameters and the specification arecomputed. The specification and a receptible error could be inputted bya tester, and the products should be discarded if their errors exceedthe receptible error. In step 36, the present invention ends.

FIG. 4 shows a reconstruction flow of the eye diagram according to thepresent invention, and FIG. 5 shows a hint diagram of an eye diagram. Instep 41, the present invention starts. In step 42, a means of thecaptured signals 52 is computed. For example, the captured signals arefirst added together, and then averaged by their number. In step 43, themeans is used to compute the positions of zero-crossing points (such asposition 51 as shown in FIG. 5) acting as reference points. In step 44,a known data rate is used as an overlapping time T, and the sampled dataare interlaced by a period Δt (a reciprocal of the sampling frequency ofthe digitizer). By the above described, a series of sampled data can beoverlapped into one cycle time so as to generate an eye diagram. In step45, the present invention ends.

The above-described embodiments of the present invention are intended tobe illustrative only. Numerous alternative embodiments may be devised bythose skilled in the art without departing from the scope of thefollowing claims.

What is claimed is:
 1. A method for testing eye diagram characteristics,comprising the following steps: sending a precondition from a mainframeto a chip under test, and reading resulting GLPF signals from the chipunder test; digitizing and normalizing the GLPF signals; reconstructingan eye diagram according to the normalized GLPF signals; analyzing anerror between parameters of the eye diagram and a predefinedspecification; and deciding if the chip under test is valid according tothe error analysis.
 2. The method of claim 1, wherein the parameters ofthe eye diagram include a width of the eye diagram, a height of the eyediagram, a cross ratio of the eye diagram and a RMS-Jitter of the eyediagram.
 3. The method of claim 1, wherein the step of reconstructingthe eye diagram includes the following steps: computing an average valueof the normalized GLPF signals; computing positions of zero-crossingpoints according to the average value; and utilizing a transmission rateof the GLPF signals as a cycle time of the eye diagram and overlapping aseries of GLPF signals into a cycle period of the eye diagram.
 4. Anapparatus for testing eye diagram characteristics, comprising: amainframe, including: (a) a digitizer for capturing GLPF signals of achip under test, and digitalizing and normalizing the GLPF signals; (b)an eye diagram reconstruction means for overlapping a series of GLPFsignals into a cycle period of the eye diagram; and (c) an errorcomparison means for computing if parameter errors of the eye diagramare in an allowable range; and a mechanical arm connected to themainframe for carrying the chip under test.
 5. The apparatus of claim 4,wherein the mechanical arm includes a testing plate for carrying thechip under test.
 6. The apparatus of claim 4, wherein the parameters ofthe eye diagram include a width of the eye diagram a height of the eyediagram, a cross ratio of the eye diagram and a RMS-Jitter of the eyediagram.